Integrated circuits have rapidly increased in complexity, operating speed and utility. One technique for specifying an integrated circuit design is with a hardware description language (HDL) such as VHDL. A hardware description language (HDL) enables representation of an integrated circuit design at a logical level, and provides a high level design language. An integrated circuit is represented in several different levels, comprising different layers of abstraction. Silicon compilers, comprising synthesis programs, are used to yield a final implementation wherein the programs generate sufficient detail to proceed directly to silicon fabrication.
A compiler generates a netlist of generic primitive cells during the processing of an HDL program. A netlist is a list of all the nets, or collection of pins needing to be electrically connected, in a circuit. The netlist consists of a detailed list of interconnections and logic components, and can include primitive cells such as XOR gates, NAND gates, latches and D-flip flops and their associated interconnections.
The silicon compiler first generates a netlist of independent cells, and then applies a particular cell library to the resulting generic netlist via a process called mapping. As a consequence, a dependent mapped netlist is generated which uses standard circuits that are available within a cell library and which are available to the computer system. Silicon compilers and mapping programs are well understood in the art, and are described in numerous patents including U.S. Pat. Nos. 5,406,497 and 5,831,868, which are hereby incorporated herein by reference.
As circuit complexity has grown, it has been increasing difficult and expensive to test functionality of integrated circuits. Strategies that have evolved to cope with this include design for testability (DFT), a feature placed into an integrated circuit whereby predetermined test control signals place the circuit into a test mode. Application of special test input signals from an automated test pattern generator (ATPG) to inputs to the integrated circuit results in a set of output signals. The output signals are compared to expected values in order to determine if the integrated circuit provided the expected values. When a discrepancy is noted between the output signals and the expected values, it is necessary to determine how the discrepancy arose in order to be able to propose a repair, re-design or other remedial measure.
In some types of DFT, after a test signal is used to set the integrated circuit into the test mode, sequential and combinatorial logic circuits are tested by interconnecting selected flip-flops within the integrated circuit into a shift register (also known as a “scan register”) in the test mode using multiplexers. A test vector that includes known input signals is applied to portions of the integrated circuit, and the resultant output signals are first captured in parallel in, and then serially clocked (or “scan shifted”) out of, the scan registers.
It is expensive to design and manufacture new integrated circuits. It is particularly expensive to manufacture prototype integrated circuits that do not operate as expected or desired. Accordingly, it is common to simulate operation of new designs as they are being developed in order to try to identify as many potential errors or problems as possible prior to finalizing and then manufacturing the prototype design.
Typical simulation software tools, such as those available from Mentor Graphics (Wilsonville, Oreg.) or Synopsys (Mountain View, Calif.), provide a text file output containing information regarding simulated scan shifting. A great deal of time and effort is often involved in tracing back from error flags in these text files, using netlist parsing and calculations, to determine where the problem actually lies. This process is also sufficiently complex that it is error-prone, at least in part because this process fails to provide any intuitive grasp of where the problem lies.
Problems that may occur during simulated output signal capture include bad sampling by the flip-flop during a capture cycle, due to a race condition or other problem, improper clocking behavior and improper reset behavior, both of which latter conditions may be caused by clock signal spikes. Problems that may occur during simulated scan shifting include clock skew issues leading to data loss in the register, an unexpected reset that destroys some scan data, a missing clock pulse due to dysfunctional clock gating or interruption of the scan chain, which may be due to bad gating or multiplexing.
What is needed is a tool that provides an intuitive understanding of signal flow in automated simulation of new integrated circuit designs, and that promotes ready and rapid discrimination between simulated shift-induced errors and simulated signal capture errors in integrated circuit designs incorporating design for testability.